parallel 2013 » Agenda »

// Hardware transactional memory: what developers need to know now

Utilizing full multicore potential is a challenge because of the hindering concurrent access to shared data. Software Transactional Memory (S-TM) is considered as a better concurrency control but its usage was limited because of the overhead. With the introduction of transactional synchronization support already in entry hardware (Intel 4th-gen Core architecture) using TM becomes practical. We present hardware TM capabilities on the example of Intel Transactional Synchronization Extensions and show how developers can now implement scalable and less error-prone synchronization using them.

Attendees need basic understanding of common thread synchronization mechanisms such as mutexes and read-write locks.

// Referent

// Roman Dementiev

owns Masters and PhD degrees from Saarland University, Germany, with the focus on efficient algorithms and software libraries. Currently he is at Intel working on optimization of commercial enterprise software for advanced hardware architectures also helping to define future Intel technologies.