Intel Transactional Synchronization Extensions (Intel TSX) is an extension of instruction set architecture introduced in the microarchitecture code name Haswell. Intel TSX specifies hardware support for speculative execution of critical sections (lock elision), which is a simpler mechanism for scalable concurrent data access as opposed to inherently complex fine-grained locking or lock-free algorithms.
We will cover methods to apply Intel TSX using standard frameworks (PTHREADS, Intel TBB, OpenMP) and also explain tuning workflows quantifying and diagnosing transactional execution using hardware monitoring events and emulation. We will teach most important tips and tricks for increasing performance using Intel TSX. We overview TSX usage scenarios and obtained performance gains in HPC, generic concurrent data structures, and also real database products when running on Intel Xeon E7 processors with Intel TSX support.
Skills
Thread synchronization primitives, mutexes, read/write locks, lock-free algorithms, atomic instructions.
Lernziele
The session is to teach easy-to-implement scalable data structures and algorithms using Intel Transactional Synchronization Extensions and share experience from integration of Intel TSX into software products.
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Roman Dementiev
owns Masters and PhD degrees from Saarland University, Germany, with the focus on efficient algorithms and software libraries. Currently he is at Intel working on optimization of commercial enterprise software for advanced hardware architectures also helping to define future Intel technologies.